pci_regs.h

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/* @JUNGO_COPYRIGHT@ */
 
#ifndef _PCI_REGS_H_
#define _PCI_REGS_H_
 
/*****************************************************************************
* File - pci_regs.h - PCI configuration space and address spaces definitions *
******************************************************************************/
 
/* -------------------------
 * Register type definitions
 * ------------------------- */
 
typedef enum
{
    HEADER_TYPE_NORMAL = 0x01,
    HEADER_TYPE_BRIDGE = 0x02,
    HEADER_TYPE_CARDBUS = 0x04,
    HEADER_TYPE_NRML_BRIDGE = HEADER_TYPE_NORMAL | HEADER_TYPE_BRIDGE,
    HEADER_TYPE_NRML_CARDBUS = HEADER_TYPE_NORMAL | HEADER_TYPE_CARDBUS,
    HEADER_TYPE_BRIDGE_CARDBUS = HEADER_TYPE_BRIDGE | HEADER_TYPE_CARDBUS,
    HEADER_TYPE_ALL =
        HEADER_TYPE_NORMAL | HEADER_TYPE_BRIDGE | HEADER_TYPE_CARDBUS
} WDC_PCI_HEADER_TYPE;
 
/* -----------------------------------------------
    PCI configuration registers offsets
   ----------------------------------------------- */
typedef enum {
    PCI_VID   = 0x00, 
    PCI_DID   = 0x02, 
    PCI_CR    = 0x04, 
    PCI_SR    = 0x06, 
    PCI_REV   = 0x08, 
    PCI_CCR   = 0x09, 
    PCI_CCSC  = 0x0a, 
    PCI_CCBC  = 0x0b, 
    PCI_CLSR  = 0x0c, 
    PCI_LTR   = 0x0d, 
    PCI_HDR   = 0x0e, 
    PCI_BISTR = 0x0f, 
    PCI_BAR0  = 0x10, 
    PCI_BAR1  = 0x14, 
    PCI_BAR2  = 0x18, 
    PCI_BAR3  = 0x1c, 
    PCI_BAR4  = 0x20, 
    PCI_BAR5  = 0x24, 
    PCI_CIS   = 0x28, 
    PCI_SVID  = 0x2c, 
    PCI_SDID  = 0x2e, 
    PCI_EROM  = 0x30, 
    PCI_CAP   = 0x34, 
    PCI_ILR   = 0x3c, 
    PCI_IPR   = 0x3d, 
    PCI_MGR   = 0x3e, 
    PCI_MLR   = 0x3f  
} PCI_CONFIG_REGS_OFFSET;
 
typedef enum
{
    PCIE_CAP_ID   = 0x0,
    NEXT_CAP_PTR = 0x1,
    CAP_REG      = 0x2,
    DEV_CAPS     = 0x4,
    DEV_CTL      = 0x8,
    DEV_STS      = 0xa,
    LNK_CAPS     = 0xc,
    LNK_CTL      = 0x10,
    LNK_STS      = 0x12,
    SLOT_CAPS    = 0x14,
    SLOT_CTL     = 0x18,
    SLOT_STS     = 0x1a,
    ROOT_CAPS    = 0x1c,
    ROOT_CTL     = 0x1e,
    ROOT_STS     = 0x20,
    DEV_CAPS2    = 0x24,
    DEV_CTL2     = 0x28,
    DEV_STS2     = 0x2a,
    LNK_CAPS2    = 0x2c,
    LNK_CTL2     = 0x30,
    LNK_STS2     = 0x32,
    SLOT_CAPS2   = 0x34,
    SLOT_CTL2    = 0x38,
    SLOT_STS2    = 0x3a
} PCIE_CONFIG_REGS_OFFSET;
 
#define PCI_HEADER_TYPE     0x0e    
#define  PCI_HEADER_TYPE_NORMAL  0
#define  PCI_HEADER_TYPE_BRIDGE  1
#define  PCI_HEADER_TYPE_CARDBUS 2
 
#define PCI_SR_CAP_LIST_BIT 0x00000010
 
typedef enum {
    AD_PCI_BAR0 = 0,
    AD_PCI_BAR1 = 1,
    AD_PCI_BAR2 = 2,
    AD_PCI_BAR3 = 3,
    AD_PCI_BAR4 = 4,
    AD_PCI_BAR5 = 5,
    AD_PCI_BARS = 6
} AD_PCI_BAR;
 
/* PCI basic and extended capability lists last updated from-
 *     PCI Code and ID Assignment Specification Revision 1.5 */
/* Some of the following strings and macros are taken from
 * include/uapi/linux/pci_regs.h in Linux Kernel source */
/* Capability lists */
#define  PCI_CAP_LIST_ID    0     
#define  PCI_CAP_ID_PM      0x01  
#define  PCI_CAP_ID_AGP     0x02  
#define  PCI_CAP_ID_VPD     0x03  
#define  PCI_CAP_ID_SLOTID  0x04  
#define  PCI_CAP_ID_MSI     0x05  
#define  PCI_CAP_ID_CHSWP   0x06  
#define  PCI_CAP_ID_PCIX    0x07  
#define  PCI_CAP_ID_HT      0x08  
#define  PCI_CAP_ID_VNDR    0x09  
#define  PCI_CAP_ID_DBG     0x0A  
#define  PCI_CAP_ID_CCRC    0x0B  
#define  PCI_CAP_ID_SHPC    0x0C  
#define  PCI_CAP_ID_SSVID   0x0D  
#define  PCI_CAP_ID_AGP3    0x0E  
#define  PCI_CAP_ID_SECDEV  0x0F  
#define  PCI_CAP_ID_EXP     0x10  
#define  PCI_CAP_ID_MSIX    0x11  
#define  PCI_CAP_ID_SATA    0x12  
#define  PCI_CAP_ID_AF      0x13  
#define  PCI_CAP_LIST_NEXT  1     
/* Extended Capabilities (PCI-X 2.0 and Express) */
#define PCI_EXT_CAP_ID(header)          (header & 0x0000ffff)
#define PCI_EXT_CAP_VER(header)         ((header >> 16) & 0xf)
#define PCI_EXT_CAP_NEXT(header)        ((header >> 20) & 0xffc)
 
#define PCI_EXT_CAP_ID_ERR      0x0001  
#define PCI_EXT_CAP_ID_VC       0x0002  
#define PCI_EXT_CAP_ID_DSN      0x0003  
#define PCI_EXT_CAP_ID_PWR      0x0004  
#define PCI_EXT_CAP_ID_RCLD     0x0005  
#define PCI_EXT_CAP_ID_RCILC    0x0006  
#define PCI_EXT_CAP_ID_RCEC     0x0007  
#define PCI_EXT_CAP_ID_MFVC     0x0008  
#define PCI_EXT_CAP_ID_VC9      0x0009  
#define PCI_EXT_CAP_ID_RCRB     0x000A  
#define PCI_EXT_CAP_ID_VNDR     0x000B  
#define PCI_EXT_CAP_ID_CAC      0x000C  
#define PCI_EXT_CAP_ID_ACS      0x000D  
#define PCI_EXT_CAP_ID_ARI      0x000E  
#define PCI_EXT_CAP_ID_ATS      0x000F  
#define PCI_EXT_CAP_ID_SRIOV    0x0010  
#define PCI_EXT_CAP_ID_MRIOV    0x0011  
#define PCI_EXT_CAP_ID_MCAST    0x0012  
#define PCI_EXT_CAP_ID_PRI      0x0013  
#define PCI_EXT_CAP_ID_AMD_XXX  0x0014  
#define PCI_EXT_CAP_ID_REBAR    0x0015  
#define PCI_EXT_CAP_ID_DPA      0x0016  
#define PCI_EXT_CAP_ID_TPH      0x0017  
#define PCI_EXT_CAP_ID_LTR      0x0018  
#define PCI_EXT_CAP_ID_SECPCI   0x0019  
#define PCI_EXT_CAP_ID_PMUX     0x001A  
#define PCI_EXT_CAP_ID_PASID    0x001B  
#define PCI_EXT_CAP_ID_LNR      0x001C  
#define PCI_EXT_CAP_ID_DPC      0x001D  
#define PCI_EXT_CAP_ID_L1PMS    0x001E  
#define PCI_EXT_CAP_ID_PTM      0x001F  
#define PCI_EXT_CAP_ID_MPHY     0x0020  
#define PCI_EXT_CAP_ID_FRSQ     0x0021  
#define PCI_EXT_CAP_ID_RTR      0x0022  
#define GET_CAPABILITY_STR(cap_id) \
    (cap_id) == 0x00 ? "Null Capability" : \
    (cap_id) == PCI_CAP_ID_PM ? "Power Management" : \
    (cap_id) == PCI_CAP_ID_AGP ? "Accelerated Graphics Port" : \
    (cap_id) == PCI_CAP_ID_VPD ? "Vital Product Data" : \
    (cap_id) == PCI_CAP_ID_SLOTID ? "Slot Identification" : \
    (cap_id) == PCI_CAP_ID_MSI ? "Message Signalled Interrupts (MSI)" : \
    (cap_id) == PCI_CAP_ID_CHSWP ? "CompactPCI HotSwap" : \
    (cap_id) == PCI_CAP_ID_PCIX ? "PCI-X" : \
    (cap_id) == PCI_CAP_ID_HT ? "HyperTransport" : \
    (cap_id) == PCI_CAP_ID_VNDR ? "Vendor-Specific" : \
    (cap_id) == PCI_CAP_ID_DBG ? "Debug port" : \
    (cap_id) == PCI_CAP_ID_CCRC ? "CompactPCI Central Resource Control" : \
    (cap_id) == PCI_CAP_ID_SHPC ? "PCI Standard Hot-Plug Controller" : \
    (cap_id) == PCI_CAP_ID_SSVID ? "Bridge subsystem vendor/device ID" : \
    (cap_id) == PCI_CAP_ID_AGP3 ? "AGP Target PCI-PCI bridge" : \
    (cap_id) == PCI_CAP_ID_SECDEV ? "Secure Device" : \
    (cap_id) == PCI_CAP_ID_EXP ? "PCI Express" : \
    (cap_id) == PCI_CAP_ID_MSIX ? "Extended Message Signalled Interrupts (MSI-X)" : \
    (cap_id) == PCI_CAP_ID_SATA ? "SATA Data/Index Conf." : \
    (cap_id) == PCI_CAP_ID_AF ? "PCI Advanced Features" : \
    "Unknown"
 
#define GET_EXTENDED_CAPABILITY_STR(cap_id) \
    (cap_id) == 0x0000 ? "Null Capability" : \
    (cap_id) == PCI_EXT_CAP_ID_ERR ? "Advanced Error Reporting (AER)" : \
    (cap_id) == PCI_EXT_CAP_ID_VC ? "Virtual Channel (VC)" :  \
    (cap_id) == PCI_EXT_CAP_ID_DSN ? "Device Serial Number" : \
    (cap_id) == PCI_EXT_CAP_ID_PWR ? "Power Budgeting" : \
    (cap_id) == PCI_EXT_CAP_ID_RCLD ? "Root Complex Link Declaration" : \
    (cap_id) == PCI_EXT_CAP_ID_RCILC ? "Root Complex Internal Link Control" : \
    (cap_id) == PCI_EXT_CAP_ID_RCEC ? "Root Complex Event Collector Endpoint Association" : \
    (cap_id) == PCI_EXT_CAP_ID_MFVC ? "Multi-Function Virtual Channel (MFVC)" : \
    (cap_id) == PCI_EXT_CAP_ID_VC9 ? "Virtual Channel (VC)" :  \
    (cap_id) == PCI_EXT_CAP_ID_RCRB ? "Root Complex Register Block (RCRB) Header" : \
    (cap_id) == PCI_EXT_CAP_ID_VNDR ? "Vendor-Specific Extended Capability (VSEC)" : \
    (cap_id) == PCI_EXT_CAP_ID_CAC ? "Configuration Access Correlation (CAC)" : \
    (cap_id) == PCI_EXT_CAP_ID_ACS ? "Access Control Services (ACS)" : \
    (cap_id) == PCI_EXT_CAP_ID_ARI ? "Alternative Routing-ID Interpretation (ARI)" : \
    (cap_id) == PCI_EXT_CAP_ID_ATS ? "Address Translation Services (ATS)" : \
    (cap_id) == PCI_EXT_CAP_ID_SRIOV ? "Single Root I/O Virtualization (SR-IOV)" : \
    (cap_id) == PCI_EXT_CAP_ID_MRIOV ? "Multi-Root I/O Virtualization (MR-IOV)" : \
    (cap_id) == PCI_EXT_CAP_ID_MCAST ? "Multicast" : \
    (cap_id) == PCI_EXT_CAP_ID_PRI ? "Page Request" : \
    (cap_id) == PCI_EXT_CAP_ID_AMD_XXX ? "Reserved for AMD" : \
    (cap_id) == PCI_EXT_CAP_ID_REBAR ? "Resizable BAR" : \
    (cap_id) == PCI_EXT_CAP_ID_DPA ? "Dynamic Power Allocation (DPA)" : \
    (cap_id) == PCI_EXT_CAP_ID_TPH ? "TLP Processing Hints (TPH)" : \
    (cap_id) == PCI_EXT_CAP_ID_LTR ? "Latency Tolerance Reporting (LTR)" : \
    (cap_id) == PCI_EXT_CAP_ID_SECPCI ? "Secondary PCI Express" : \
    (cap_id) == PCI_EXT_CAP_ID_PMUX ? "Protocol Multiplexing (PMUX)" : \
    (cap_id) == PCI_EXT_CAP_ID_PASID ? "Process Address Space ID (PASID)" : \
    (cap_id) == PCI_EXT_CAP_ID_LNR ? "LN Requester (LNR)" : \
    (cap_id) == PCI_EXT_CAP_ID_L1PMS ? "Downstream Port Containment (DPC)" : \
    (cap_id) == PCI_EXT_CAP_ID_L1PMS ? "L1 PM Substates" : \
    (cap_id) == PCI_EXT_CAP_ID_PTM ? "Precision Time Measurement (PTM)" : \
    (cap_id) == PCI_EXT_CAP_ID_MPHY ? "PCI Express over M-PHY (M-PCIe)" : \
    (cap_id) == PCI_EXT_CAP_ID_FRSQ ? "FRS Queueing" : \
    (cap_id) == PCI_EXT_CAP_ID_RTR ? "Readiness Time Reporting" : \
    "Unknown"
 
#define PCI_EXP_DEVCAP_PHANTOM_SHIFT 3
#define PCI_STATUS_DEVSEL_SHIFT      9
#define PCI_EXP_DEVCTL_READRQ_SHIFT  12
#define PCI_EXP_SLTCAP_SPLV_SHIFT    7
#define PCI_EXP_FLAGS_TYPE_SHIFT     9
#define PCI_EXP_DEVCAP_L1_SHIFT      9
#define PCI_EXP_DEVCAP_PWD_SCL_SHIFT 26
#define PCI_EXP_DEVCAP_PWR_VAL_SHIFT 18
#define PCI_EXP_DEVCTL_PAYLOAD_SHIFT 5
#define PCI_EXP_LNKCAP_MLW_SHIFT     4
#define PCI_EXP_LNKCAP_ASPMS_SHIFT   10
#define PCI_EXP_LNKCAP_L0SEL_SHIFT   12
#define PCI_EXP_LNKCAP_L1EL_SHIFT    15
#define PCI_EXP_SLTCAP_SPLS_SHIFT    15
#define PCI_EXP_SLTCAP_AIC_SHIFT     6
#define PCI_EXP_SLTCTL_PIC_SHIFT     8
#define PCI_EXP_DEVCAP2_EE_TLP_PREFIX_SUPP_SHIFT 22
#define PCI_EXP_LNKCTL2_TRANS_MARGIN_MASK_SHIFT  22
 
#define PCI_COMMAND     0x04    
#define  PCI_COMMAND_IO     0x1 
#define  PCI_COMMAND_MEMORY 0x2 
#define  PCI_COMMAND_MASTER 0x4 
#define  PCI_COMMAND_SPECIAL    0x8 
#define  PCI_COMMAND_INVALIDATE 0x10    
#define  PCI_COMMAND_VGA_PALETTE 0x20   
#define  PCI_COMMAND_PARITY 0x40    
#define  PCI_COMMAND_WAIT   0x80    
#define  PCI_COMMAND_SERR   0x100   
#define  PCI_COMMAND_FAST_BACK  0x200   
#define  PCI_COMMAND_INTX_DISABLE 0x400 
#define PCI_STATUS      0x06    
#define  PCI_STATUS_INTERRUPT 0x08 
#define  PCI_STATUS_CAP_LIST  0x10 
#define  PCI_STATUS_66MHZ     0x20 
#define  PCI_STATUS_UDF       0x40 
#define  PCI_STATUS_FAST_BACK     0x80    
#define  PCI_STATUS_PARITY        0x100   
#define  PCI_STATUS_DEVSEL_MASK   0x600   
#define  PCI_STATUS_DEVSEL_FAST   0x000
#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
#define  PCI_STATUS_DEVSEL_SLOW   0x400
#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 
#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 
#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 
#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 
#define  PCI_STATUS_DETECTED_PARITY  0x8000 
#
/* PCI Express capability registers */
 
#define PCI_EXP_FLAGS   2 
#define PCI_EXP_FLAGS_VERS  0x000f 
#define PCI_EXP_FLAGS_TYPE  0x00f0 
#define  PCI_EXP_TYPE_ENDPOINT    0x0 
#define  PCI_EXP_TYPE_LEG_END     0x1 
#define  PCI_EXP_TYPE_ROOT_PORT   0x4 
#define  PCI_EXP_TYPE_UPSTREAM    0x5 
#define  PCI_EXP_TYPE_DOWNSTREAM  0x6 
#define  PCI_EXP_TYPE_PCI_BRIDGE  0x7 
#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8 
#define  PCI_EXP_TYPE_RC_END      0x9 
#define  PCI_EXP_TYPE_RC_EC       0xa 
#define PCI_EXP_FLAGS_SLOT  0x0100  
#define PCI_EXP_FLAGS_IRQ   0x3e00  
#define PCI_EXP_DEVCAP  4
#define  PCI_EXP_DEVCAP_PAYLOAD 0x00000007 
#define  PCI_EXP_DEVCAP_PHANTOM 0x00000018 
#define  PCI_EXP_DEVCAP_EXT_TAG 0x00000020 
#define  PCI_EXP_DEVCAP_L0S     0x000001c0 
#define  PCI_EXP_DEVCAP_L1      0x00000e00 
#define  PCI_EXP_DEVCAP_ATN_BUT 0x00001000 
#define  PCI_EXP_DEVCAP_ATN_IND 0x00002000 
#define  PCI_EXP_DEVCAP_PWR_IND 0x00004000 
#define  PCI_EXP_DEVCAP_RBER    0x00008000 
#define  PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 
#define  PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 
#define  PCI_EXP_DEVCAP_FLR     0x10000000 
#define PCI_EXP_DEVCTL      8   
#define  PCI_EXP_DEVCTL_CERE     0x0001 
#define  PCI_EXP_DEVCTL_NFERE    0x0002 
#define  PCI_EXP_DEVCTL_FERE     0x0004 
#define  PCI_EXP_DEVCTL_URRE     0x0008 
#define  PCI_EXP_DEVCTL_RELAX_EN 0x0010 
#define  PCI_EXP_DEVCTL_PAYLOAD  0x00e0 
#define  PCI_EXP_DEVCTL_EXT_TAG  0x0100 
#define  PCI_EXP_DEVCTL_PHANTOM  0x0200 
#define  PCI_EXP_DEVCTL_AUX_PME  0x0400 
#define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  
#define  PCI_EXP_DEVCTL_READRQ   0x7000 
#define  PCI_EXP_DEVCTL_READRQ_128B  0x0000 
#define  PCI_EXP_DEVCTL_READRQ_256B  0x1000 
#define  PCI_EXP_DEVCTL_READRQ_512B  0x2000 
#define  PCI_EXP_DEVCTL_READRQ_1024B 0x3000 
#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  
#define PCI_EXP_DEVSTA      10  
#define  PCI_EXP_DEVSTA_CED     0x0001  
#define  PCI_EXP_DEVSTA_NFED    0x0002  
#define  PCI_EXP_DEVSTA_FED     0x0004  
#define  PCI_EXP_DEVSTA_URD     0x0008  
#define  PCI_EXP_DEVSTA_AUXPD   0x0010  
#define  PCI_EXP_DEVSTA_TRPND   0x0020  
#define PCI_EXP_LNKCAP      12  
#define  PCI_EXP_LNKCAP_SLS 0x0000000f 
#define  PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 
#define  PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 
#define  PCI_EXP_LNKCAP_MLW 0x000003f0 
#define  PCI_EXP_LNKCAP_ASPMS   0x00000c00 
#define  PCI_EXP_LNKCAP_L0SEL   0x00007000 
#define  PCI_EXP_LNKCAP_L1EL    0x00038000 
#define  PCI_EXP_LNKCAP_CLKPM   0x00040000 
#define  PCI_EXP_LNKCAP_SDERC   0x00080000 
#define  PCI_EXP_LNKCAP_DLLLARC 0x00100000 
#define  PCI_EXP_LNKCAP_LBNC    0x00200000 
#define  PCI_EXP_LNKCAP_PN  0xff000000 
#define PCI_EXP_LNKCTL      16 
#define  PCI_EXP_LNKCTL_ASPMC     0x0003 
#define  PCI_EXP_LNKCTL_ASPM_L0S  0x0001 
#define  PCI_EXP_LNKCTL_ASPM_L1   0x0002 
#define  PCI_EXP_LNKCTL_RCB       0x0008 
#define  PCI_EXP_LNKCTL_LD        0x0010 
#define  PCI_EXP_LNKCTL_RL        0x0020 
#define  PCI_EXP_LNKCTL_CCC       0x0040 
#define  PCI_EXP_LNKCTL_ES        0x0080 
#define  PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 
#define  PCI_EXP_LNKCTL_HAWD      0x0200 
#define  PCI_EXP_LNKCTL_LBMIE     0x0400 
#define  PCI_EXP_LNKCTL_LABIE   0x0800 
#define PCI_EXP_LNKSTA      18 
#define  PCI_EXP_LNKSTA_CLS 0x000f 
#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 
#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 
#define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 
#define  PCI_EXP_LNKSTA_NLW     0x03f0 
#define  PCI_EXP_LNKSTA_NLW_X1  0x0010  
#define  PCI_EXP_LNKSTA_NLW_X2  0x0020  
#define  PCI_EXP_LNKSTA_NLW_X4  0x0040  
#define  PCI_EXP_LNKSTA_NLW_X8  0x0080  
#define  PCI_EXP_LNKSTA_NLW_SHIFT 4 
#define  PCI_EXP_LNKSTA_LT      0x0800  
#define  PCI_EXP_LNKSTA_SLC     0x1000  
#define  PCI_EXP_LNKSTA_DLLLA   0x2000  
#define  PCI_EXP_LNKSTA_LBMS    0x4000  
#define  PCI_EXP_LNKSTA_LABS    0x8000  
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1  20  
#define PCI_EXP_SLTCAP      20  
#define  PCI_EXP_SLTCAP_ABP 0x00000001 
#define  PCI_EXP_SLTCAP_PCP 0x00000002 
#define  PCI_EXP_SLTCAP_MRLSP   0x00000004 
#define  PCI_EXP_SLTCAP_AIP 0x00000008 
#define  PCI_EXP_SLTCAP_PIP 0x00000010 
#define  PCI_EXP_SLTCAP_HPS 0x00000020 
#define  PCI_EXP_SLTCAP_HPC 0x00000040 
#define  PCI_EXP_SLTCAP_SPLV    0x00007f80 
#define  PCI_EXP_SLTCAP_SPLS    0x00018000 
#define  PCI_EXP_SLTCAP_EIP 0x00020000 
#define  PCI_EXP_SLTCAP_NCCS    0x00040000 
#define  PCI_EXP_SLTCAP_PSN 0xfff80000 
#define PCI_EXP_SLTCTL      24 
#define  PCI_EXP_SLTCTL_ABPE    0x0001  
#define  PCI_EXP_SLTCTL_PFDE    0x0002  
#define  PCI_EXP_SLTCTL_MRLSCE  0x0004  
#define  PCI_EXP_SLTCTL_PDCE    0x0008  
#define  PCI_EXP_SLTCTL_CCIE    0x0010  
#define  PCI_EXP_SLTCTL_HPIE    0x0020  
#define  PCI_EXP_SLTCTL_AIC 0x00c0  
#define  PCI_EXP_SLTCTL_ATTN_IND_ON    0x0040 
#define  PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 
#define  PCI_EXP_SLTCTL_ATTN_IND_OFF   0x00c0 
#define  PCI_EXP_SLTCTL_PIC 0x0300  
#define  PCI_EXP_SLTCTL_PWR_IND_ON     0x0100 
#define  PCI_EXP_SLTCTL_PWR_IND_BLINK  0x0200 
#define  PCI_EXP_SLTCTL_PWR_IND_OFF    0x0300 
#define  PCI_EXP_SLTCTL_PCC 0x0400  
#define  PCI_EXP_SLTCTL_PWR_ON         0x0000 
#define  PCI_EXP_SLTCTL_PWR_OFF        0x0400 
#define  PCI_EXP_SLTCTL_EIC 0x0800  
#define  PCI_EXP_SLTCTL_DLLSCE  0x1000  
#define PCI_EXP_SLTSTA      26 
#define  PCI_EXP_SLTSTA_ABP     0x0001  
#define  PCI_EXP_SLTSTA_PFD     0x0002  
#define  PCI_EXP_SLTSTA_MRLSC   0x0004  
#define  PCI_EXP_SLTSTA_PDC     0x0008  
#define  PCI_EXP_SLTSTA_CC      0x0010  
#define  PCI_EXP_SLTSTA_MRLSS   0x0020  
#define  PCI_EXP_SLTSTA_PDS     0x0040  
#define  PCI_EXP_SLTSTA_EIS     0x0080  
#define  PCI_EXP_SLTSTA_DLLSC   0x0100  
#define PCI_EXP_RTCTL       28  
#define  PCI_EXP_RTCTL_SECEE    0x0001  
#define  PCI_EXP_RTCTL_SENFEE   0x0002  
#define  PCI_EXP_RTCTL_SEFEE    0x0004  
#define  PCI_EXP_RTCTL_PMEIE    0x0008  
#define  PCI_EXP_RTCTL_CRSSVE   0x0010  
#define PCI_EXP_RTCAP       30  
#define  PCI_EXP_RTCAP_CRSVIS   0x0001  
#define PCI_EXP_RTSTA       32  
#define PCI_EXP_RTSTA_PME       0x00010000 
#define PCI_EXP_RTSTA_PENDING   0x00020000 
#define PCI_EXP_DEVCAP2     36  
#define PCI_EXP_DEVCAP2_RANGE_A 0x1 
#define PCI_EXP_DEVCAP2_RANGE_B 0x2 
#define PCI_EXP_DEVCAP2_RANGE_C 0x4 
#define PCI_EXP_DEVCAP2_RANGE_D 0x8 
#define PCI_EXP_DEVCAP2_COMP_TO_RANGES_SUPP 0xF
#define PCI_EXP_DEVCAP2_COMP_TO_DIS_SUPP    0x000010
#define  PCI_EXP_DEVCAP2_ARI        0x00000020 
#define  PCI_EXP_DEVCAP2_ATOMIC_ROUTE   0x00000040 
#define PCI_EXP_DEVCAP2_ATOMIC_COMP32      0x000080
#define PCI_EXP_DEVCAP2_ATOMIC_COMP64   0x00000100 
#define PCI_EXP_DEVCAP2_128_CAS_COMP_SUPP   0x000200
#define PCI_EXP_DEVCAP2_NO_RO_ENABLED_PR    0x000400
#define  PCI_EXP_DEVCAP2_LTR        0x00000800 
#define PCI_EXP_DEVCAP2_TPH_COMP_SUPP       0x001000
#define PCI_EXP_DEVCAP2_EXT_TPH_COMP_SUPP   0x002000
#define  PCI_EXP_DEVCAP2_OBFF_MASK  0x000c0000 
#define  PCI_EXP_DEVCAP2_OBFF_MSG   0x00040000 
#define  PCI_EXP_DEVCAP2_OBFF_WAKE  0x00080000 
#define PCI_EXP_DEVCAP2_EXT_FMT_FIELD_SUPP  0x100000
#define PCI_EXP_DEVCAP2_EE_TLP_PREFIX_SUPP  0x200000
#define PCI_EXP_DEVCAP2_MAX_EE_TLP_PREFIXES 0xC00000
#define PCI_EXP_DEVCTL2     40  
#define PCI_EXP_DEVCTL2_COMP_TIMEOUT_DISABLE 0x0010
#define  PCI_EXP_DEVCTL2_COMP_TIMEOUT   0x000f  
#define  PCI_EXP_DEVCTL2_ARI        0x0020  
#define PCI_EXP_DEVCTL2_ATOMIC_REQ  0x0040  
#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 
#define  PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100  
#define  PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200  
#define  PCI_EXP_DEVCTL2_LTR_EN     0x0400  
#define  PCI_EXP_DEVCTL2_OBFF_MSGA_EN   0x2000  
#define  PCI_EXP_DEVCTL2_OBFF_MSGB_EN   0x4000  
#define  PCI_EXP_DEVCTL2_OBFF_WAKE_EN   0x6000  
#define  PCI_EXP_DEVCTL2_EE_TLP_PREFIX_BLOCK  0x8000
#define PCI_EXP_DEVSTA2                 42  
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2  44  
#define PCI_EXP_LNKCAP2                 44  
#define  PCI_EXP_LNKCAP2_SLS_2_5GB  0x00000002 
#define  PCI_EXP_LNKCAP2_SLS_5_0GB  0x00000004 
#define  PCI_EXP_LNKCAP2_SLS_8_0GB  0x00000008 
#define  PCI_EXP_LNKCAP2_CROSSLINK  0x00000100 
#define PCI_EXP_LNKCTL2                 48  
#define  PCI_EXP_LNKCTL2_LNK_SPEED_2_5       0x00000001 
#define  PCI_EXP_LNKCTL2_LNK_SPEED_5_0       0x00000002 
#define  PCI_EXP_LNKCTL2_LNK_SPEED_8_0       0x00000003 
#define  PCI_EXP_LNKCTL2_TRGT_LNK_SPEED_MASK 0x0000000f
#define  PCI_EXP_LNKCTL2_ENTER_COMP          0x00000010 
#define  PCI_EXP_LNKCTL2_HW_AUTO_SPEED_DIS   0x00000020
#define  PCI_EXP_LNKCTL2_SELECTABLE_DEEMPH   0x00000040
#define  PCI_EXP_LNKCTL2_TRANS_MARGIN_MASK   0x00000380 
#define  PCI_EXP_LNKCTL2_ENTER_MOD_COMP      0x00000400
#define  PCI_EXP_LNKCTL2_COMP_SOS            0x00000800 
#define  PCI_EXP_LNKCTL2_DEEMPH_LVL_POLL     0x00001000
#define  PCI_EXP_LNKCTL2_TRANS_PRESENT_POLL  0x0000f000
#define PCI_EXP_LNKSTA2 50
#define  PCI_EXP_LNKSTA2_CDL        0x00000001
#define  PCI_EXP_LNKSTA2_EQUALIZ_COMP 0x00000002 
#define  PCI_EXP_LNKSTA2_EQUALIZ_PH1 0x00000004 
#define  PCI_EXP_LNKSTA2_EQUALIZ_PH2 0x00000008 
#define  PCI_EXP_LNKSTA2_EQUALIZ_PH3 0x00000010 
#define  PCI_EXP_LNKSTA2_LINE_EQ_REQ 0x00000020 
#define PCI_EXP_SLTCAP2 52  
#define PCI_EXP_SLTCTL2 56  
#define PCI_EXP_SLTSTA2 58  
#endif /* _PCI_REGS_H_ */